(a) Field of the Invention
The present invention relates to a high voltage gate driver circuit.
(b) Description of the Related Art
A high voltage gate driver is a circuit for receiving a low voltage signal and controlling a high voltage element coupled to an output terminal.
FIG. 1 is a circuit diagram showing a high voltage gate driver according to previously developed techniques. As shown in FIG. 1, the conventional high voltage gate driver circuit includes transistors M1 and M2, a level shifter 11 including resistors R1 and R2, reshapers 12 and 13, an S-R latch 14, and a gate driver 15.
MOSFETs, which can withstand high voltage, are used for the transistors M1 and M2. The transistors M1 and M2 are driven by a short pulse signal in order to reduce power consumption because high voltages are applied to the transistors M1 and M2. A low voltage element having the ability to withstand approximately 20V in voltage is used for the resistors R1 and R2, the reshapers 11 and 12, the S-R latch 14, and the gate driver 15.
A conventional high voltage gate driver circuit is operated as follows. When the transistor M1 or the transistor M2 is turned on according to an external SET signal or a RESET signal, a voltage is generated on one end of the resistor R1 or the resistor R2 coupled to the reshapers 12 and 13. The reshapers 12 and 13, which have respective predetermined threshold voltages VTH, detect voltage changes across the resistors R1 and R2, and restore the SET/RESET signals that are applied in a low voltage region to a high voltage region. The output voltages of the reshapers 12 and 13 are input to the S-R latch 14. The S-R latch 14 stores a status of the SET/RESET signals. A signal output by the S-R latch 14 is input to the gate driver 15, which in turn drives a gate of a high voltage output element MO coupled to an output terminal.
The reshapers 12 and 13 have the respective threshold voltages VTH. Therefore, the reshapers 12 and 13 will only recognize the input voltages SETB and RESETB as pulse signals when the change of these input voltages exceeds the threshold voltages VTH. Accordingly, the condition VB>VBS−VTH establishes the minimum voltage VB that the reshapers 12 and 13 are able to recognize for a normal operation of the high voltage gate driver circuit.
Generally, when VTH is set to be high, in other words when VTH is near to VB, the reshapers 12 and 13 are able to operate even when VB has a lower value. However, when VTH is set to be high, noise originating from VB may occur, and the reshapers 12 and 13 may operate incorrectly. Therefore, VTH should be set as low as possible, and the reshapers 12 and 13 should be set to operate when SETB and RESETB have become low enough such that noise does not cause the reshapers 12 and 13 to operate incorrectly.
However, VB is not a fixed voltage but rather is a voltage determined by an external power source VBS and a voltage VS. More particularly, the voltage VS may go below 0V when the transistors M1 and M2 switch. This could occur when an inductor is coupled to the output terminal, or by a parasitic inductance of a wire. When the voltage VS goes below 0V, the voltage VB also decreases.
Afterward, when the SET signal is input, the transistor M1 is turned on and a SETB signal is applied to the reshaper 12. When the SETB signal swings from VB to 0V, as shown in FIG. 2, the reshaper 12 may recognize the SETB signal correctly when the threshold voltage is VTH1 (i.e., over 0V), but the reshaper 12 cannot correctly recognize the SETB signal when the threshold voltage is VTH2 (i.e., under 0V).
Moreover, when a voltage VB having a large value of dv/dt (i.e., high slope) is applied, a current for recharging a parasitic capacitor formed on the drains of the transistor M1 and transistor M2 of the level shifter 11 is generated. This current causes a voltage drop in the resistors R1 and R2. As a result, the SR latch 14 is operated by the voltage change of the resistors R1 and R2, which occurs regardless of the SET/RESET signal.